It is widely known that the speed of propagation of interconnect signals is one of the most important factors controlling overall circuit speed as feature sizes are reduced and the number of devices per unit area as well as the number of interconnect levels are increased. Throughout the semiconductor industry, there has been a strong drive to increase the aspect ratio (i.e., height to width ratio) and to reduce the dielectric constant, k, of the interlayer dielectric (ILD) materials used to electrically insulate the conductive metal lines. As a result, interconnect signals travel faster through conductors due to a reduction in resistance-capacitance (RC) delays.
State-of-the-art semiconductor chips employ copper (Cu) as the electrical conductor and inorganic organosilicates as the low dielectric constant (low-k) dielectric, and have up to twelve levels of Cu/low-k interconnect layers. These Cu/low-k interconnect layers are fabricated with an iterative additive process, called dual-damascene, which includes several processing steps. For example, a typical dual-damascene process includes film deposition, patterning by lithography and reactive ion etching, liner (Cu barrier) deposition, Cu metal fill by electrochemical plating, and chemical-mechanical polishing of excessive Cu metal; these steps are described in greater detail in the following paragraphs.
When fabricating integrated circuit wiring within a multi-layered scheme, an electrically insulating or dielectric material, e.g., silicon oxide or a low-k insulator will normally be patterned with several thousand openings to create conductive trench, i.e., line, openings and/or via openings using photo patterning and plasma etching techniques, e.g., photolithography with subsequent etching by plasma processes. The openings are typically filled with a conductive metallic material, e.g., aluminum, copper or their alloys, etc., to interconnect the active and/or passive elements of the integrated circuits. The semiconductor device is then polished to level its surface.
A continuous cap layer is then normally deposited over the planarized surface featuring the dielectric material and conductive metallic material. Next, a dielectric material is deposited over the continuous cap layer, via and line openings are created within the dielectric layer as before, another conductive metallic material is deposited within the openings and another continuous cap layer is deposited thereon. The process is repeated to fabricate a multi-layer interconnect wiring system. The multi-layer interconnect system built thereby is referred to in the art as a dual-damascene integration scheme.
Unfortunately, the strategy to introduce low-k materials (typically dielectrics whose dielectric constant is below that of silicon oxide) into advanced interconnects is difficult to implement due to the new materials chemistry of the low-k materials that are being introduced. Moreover, low-k dielectrics exhibit fundamentally weaker electrical and mechanical properties as compared to silicon oxide. Moreover, low-k dielectric alternatives are typically susceptible to damage during the various interconnect processing steps. The damage observed in the low-k dielectric materials is manifested by an increase in the dielectric constant and increased moisture uptake, which may result in reduced performance and device reliability.
One way to overcome the integration challenges of low-k materials is to protect these low-k dielectric materials by adding at least one sacrificial hardmask layer onto a surface of the low-k dielectric material. While hardmask layers serve to protect the low-k material, the presence of the sacrificial hardmask layers adds enormous process complexity as more film deposition, pattern transfer etch, and removal of hardmask layers are needed.
One way to further improve performance is to introduce so called airgap structure within the low-k dielectric material of an interconnect structure. Airgap interconnect structures are formed wherein at least one airgap (or more precisely vacuum gap) is incorporated into the dielectric part of an interconnect structure. The airgap interconnect structures are typically used as means for lowering the effective dielectric constant of the interconnect structure due to the lower dielectric constant of the air (vacuum) of 1. This lower effective dielectric constant of an interconnect structure is important in the semiconductor industry since such structures have lower capacitance associated therewith, hence improving the performance of semiconductor chips containing such airgap interconnect structures. The airgap interconnect structures can be formed by fabricating a traditional Cu/dielectric interconnect structure, forming at least one gap and followed by capping the at least on gap with a dielectric layer. Alternatively they can be formed by fabricating a Cu interconnect structure with a sacrificial dielectric and then followed by removing the sacrificial dielectric between metallic conductor features.
A state-of-the-art airgap interconnect integration process uses a so called a low temperature oxide (LTO) process to fabricate traditional Cu/dielectric interconnect structures. This LTO integration scheme employs up to eight layers of sacrificial hardmask materials to fabricate a two-layer dual-damascene interconnect structure.
For example, a via-first LTO integration for forming a dual-damascene interconnect includes the steps of: depositing a dielectric material on a substrate including a patterned conductor; forming at least one via in said dielectric material, such that at least one of the vias is positioned over the patterned conductor; depositing a layer of planarizing material on the dielectric material and in the via; depositing a layer of barrier material on the layer of planarizing material; depositing at least one layer of imaging material on the layer of barrier material; forming at least one trench in the imaging material, barrier material and planarizing material, such that the at least one trench is positioned over the via; removing the imaging material, either after or concurrently with forming the trench in the planarizing material; transferring the at least one trench to the dielectric material, such that at least one of the trenches is positioned over the via; removing the barrier material, either after or concurrently with transferring the at least one trench to the dielectric material; and removing the planarizing material.
A line-first LTO integration for forming a dual-damascene interconnect structure includes the steps of: depositing a dielectric material on a substrate including a patterned conductor; forming at least one trench in the dielectric material, such that the at least one trench is positioned over the patterned conductor; depositing a layer of planarizing material on the dielectric material and in the trench; depositing a layer of barrier material on the layer of planarizing material; depositing at least one layer of imaging material on the layer of barrier material; forming at least one via in the imaging material, barrier material and planarizing material, such that at least one of the vias is positioned over the trench and the patterned conductor; removing the imaging material, either after or concurrently with forming the via in the planarizing material; transferring the at least one via to the dielectric material, such that at least one of the vias is positioned over the trench and the patterned conductor; removing the barrier material, either after or concurrently with transferring the at least one via to the dielectric material; and removing the planarizing material.
The integration schemes, such as the LTO one mentioned above, are very complex, inefficient, and costly. For example, the via-first LTO integration scheme requires ten layers of films and twenty-one process steps to form a two-layer dual-damascene dielectric structure. In other words, 80% of the films are not needed in the final interconnect structure.
Although immensely popular in semiconductor manufacturing, the prior art dual-damascene integration scheme described above suffers from several drawbacks including: First, it constitutes a signification portion of manufacturing cost of advanced semiconductor chips as many layers, up to twelve layers for the state-of-the-art chips, are required to connect the minuscule transistors within a chip and to the printed circuit board. Second, it is a main yield detractor as the many layers of films required to form the interconnects generate chances for defect introduction and, thus, degrade manufacturing yields. Third, it is very inefficient and embodies enormous complexity. The current dual-damascene integration scheme requires many sacrificial films (80% of the film stack) to pattern and protect the fragile interlayer dielectric films from damage during processing. These sacrificial patterning and protective films have to be removed after patterning and copper plating. Fourth, the performance gain by introduction of new lower-k materials is often offset by the needs for higher-k non-sacrificial materials, such as a cap layer, a hardmask layer, or a thicker copper barrier layer. Fifth, the prior art complex dual-damascene process lengthens manufacturing turn-around time and R&D development cycle. Sixth, the plasma etching process is an expensive and often unreliable process and requires significant up-front capital investment.
In prior art interconnect structures, airgaps are introduced into the structure utilizing many additional processing steps which raise the production cost of the structure being manufactured. As such, a new method of providing an airgap-containing interconnect structure is needed which avoids the numerous steps that are used in the prior art for fabricating such an interconnect structure.